As CMOS technology continues to scale further into the sub-micron region, the width of the gate structure on metal oxide semiconductor (MOS) transistors is constantly being reduced. MOS transistor gate structures are formed using conductive materials such as metals, silicides, and doped polycrystalline silicon (polysilicon). For MOS transistor gate structures formed using doped polysilicon, metal silicides are often formed on the gate structure to reduce the sheet resistance of the gate structure and to ensure proper electrical contact. The sheet resistance of the gate structure should be as low as possible for proper MOS transistor operation. As the width of the polysilicon gate structure is reduced the sheet resistance of the gate structure rises due in part to the thinner metal silicide regions that are formed on the polysilicon gate structures using existing fabrication methods. The increased sheet resistance is becoming a major limitation of the MOS transistor performance.
The self-aligned process used to fabricate MOS transistors requires the formation of a sidewall structure prior to the formation of the transistor source/drain regions. Along with the reduction in MOS transistor gate structure width, the scaling of CMOS technology also requires that the width of the sidewall structures be reduced. The width of the sidewall structures determine how far from the edge of the gate structure the source/drain regions are located. A thermal annealing process designed to activate the source/drain regions unfortunately typically pushes the edge of the source/drain regions towards the edge of the transistor gate structure. Reducing the width of the sidewall structures is therefore limited by the thermal diffusion process that takes place during the source/drain region annealing.
As CMOS technology continues to scale there is therefore an increasing need for a method to scale the width of the sidewall spacers without causing the source/drain regions to be positioned in such a region as to negatively affect the MOS transistor.